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W536Q020/q030 voice/melody/lcd controller ( viewtalk tm series) publication release date: sep, 2001 - 1 - revision a1 general description the w536q xxx, a mem ber of viewtalk tm family, is a high-performance 4-bit micro-controller (uc) with built-in speech unit, melody unit and 40seg * 16 com lcd driver unit which includes internal regulator pump circuit and dedicated one pages lcd ram. the 4-bi t uc core contains dual clock source, 4-bit alu, two 8-bit timers, one 14 bits divider, 12 pads for input or output, 7 interrupt sources and 8-level nesting for subroutine/interrupt applications. speech unit, integrated as a single chip with maximum 32 seconds (based on 6.4k sample rate with 5 bits mdpcm), is capable of expanding to 512 seconds speech address ed by external memory w55xxx with se rial bus interface. it can be implemented with winbond power speech using mdpcm algorithm. mel ody unit provides dual tone output and can store up to 1k notes. power reduction mode is also built in to minimize power dissipation. it is ideal for games, educational toys, remote controllers, watches, clocks and other application products that incorporate both lcd display and speech. body W536Q020 w536q030 voice 20 sec 30 sec i/o pad 8i/o, 4i (ra/rb/rd) 8i/o, 4i (ra/rb/rd) wdt disable/enable (mask option) y y sub-clock rc/xtal mode (mask option) y y rd port shared as serial bus (mask option) y(1) y(1) tri-state serial bus (mask option) (3) y y cascaded voice rom through serial bus (2) n y(1) (1) share 3 pads of rd port (rd1/addr, rd2/data and rd3/clk) (2) dedicate serial bus 3 pads (addr, data and clk) to interface with w55xxx. cascaded voice rom can help to expand voice up to 512 sec by w55xxx chip. (3) tri-state serial bus mask option can float serial bus while voice playing is no active. let this mask option is disabled to get minimum power consumption in general. features ? operating voltage: 2.4 volt ~ 5.5 volt ? watch dog disabled/enabled by mask option ? dual clock operating system ? main clock with ring/crystal (400 khz to 4 mhz) ? sub-clock with 32.768 khz rc/crystal by mask option ? memory ? program rom (p-rom): 16k 20 (rom bank0) ? data ram (w-ram): 1k 4 bit (ram bank 0 is 512 nibbles from 0:000 ~0:1ff and 0:380~0:3ff are mapped to special register. ram bank f is 512 nibbles from f: 200 ~f: 3ff either data ram or dedicated to script kernel) ? lcd ram (l-ram): 160 4 bit 1 pages (ram bank1 from 260~2ff ) ? 12 input/output pads
W536Q020/q030 publication release date: sep, 2001 - 2 - revision a1 ? ports for input only: 4 pads (rd port; rd1~3 can share as serial bus for external memory w55xxx interface) ? ports for input/output: 8 pads (ra and rb port) ? power-down mode ? hold mode (except for 32khz oscillator) ? stop mode (including 32khz oscillator and release by rd or rc port) ? seven types of interrupts ? five internal interrupts (divider, timer 0, timer 1, speech, melody) ? two external interrupts (rd, ra) ? one built-in 14-bit clock frequency divider circuit ? two built-in 8-bit programmable countdown timers ? timer 0: one of two clock sources (fosc/4 or fosc/1024) can be selected ? timer 1: built-in auto-reload function includes internal timer ? built-in 18/14-bit watchdog timer for system reset. ? powerful instruction sets ? 8-level subroutine (including interrupt) nesting ? lcd driver unit capability ? vlcd higher than (vdd-0.5v) ? built-in voltage regulator to v2 pad ? 40 seg 16 com ? 1/16 or 1/8 duty, 1/5 or 1/4 bias, internal pump circuit option by special register ? com 8~ 15 and seg16~39 can be shared as general input/output by special register ? either uc rom or voice rom used as lcd picture ? speech function ? provided 640k/1m bits voice rom for W536Q020/q030 based on 5 bits mdpcm algorithm ? voice rom (v-rom) available for uc data or lcd picture data. ? maximum 8*256 label/interrupt vector (voice section number) available ? provide two types of speech busy flag to either each go or each trigger ? maximum up to 16m bits speech address capability interface with external memory w55 xxx through serial bus. ? melody function ? provide 1k notes (22bits/note) dedicated melody rom ? provide two types of melody busy flag to uc either each note or each song ? provide 6 kinds of beat, 16 kinds of tempo, and pitch range from g3# to c7 ? tremolo, triple frequency and 3 kinds of percussion available ? maximum 31 songs available ? can mix speech with melody ? multi-engine controller ? direct driving speaker/buzzer or dac output ? chip on board available
W536Q020/q030 publication release date: sep, 2001 - 3 - revision a1 block diagram xin xout x32i x32o lcd driver pc stack (8 levels) timer 0 timer 1 watch dog alu acc divide rom 16k*20bit ram 1k*4bit special register hcf hef ief evf flag1 psr0 mr0 pef flag0 lpx3 pm0 lpx2 lpx0 lpx1 port ra vlcd pump & regulator tone ra0~3 res lpx4 port rd rd0~3 lpx5 lpy0 lpy1 spc mld dual tone melody (1k notes) mld_play mld_busy speech mdpcm core spc_play spc_busy pwm1/dac rosc interrupt ,hold & stop control port rb rb0~3 vssp test voice rom (640k/1mbits) pwm/dac mix block pwm2 vddp lpxy shared_rom data seg0~39 v3,v4,v5,v6 dh1,dh2 com0~15 v2 timing generator vdd vss
W536Q020/q030 publication release date: sep, 2001 - 4 - revision a1 pad description symbol i/o function xin/rxin i input pad for main clock oscillator. it can be connected to crystal when crystal mode is selected (scr0.2=1), otherwise connect a resistor to vdd to generate main system clock while ring mode is selected (scr0.2=0 and default). oscillator can be enabled or stopped by set scr0.1 to 1 or clear to 0 separately. external capacitor connects to start oscillation and get more accurate clock when while crystal mode xout o output pad for oscillator that is connected to another crystal pad when in crystal mode. external capacitor connects to start oscillation when in crystal mode. x32i/rsub1 i 32.768 khz crystal input pad or external resistor node 1 by mask option . external 15~20pf capacitor connects to start oscillation and get more accurate clock when in crystal mode. x32o/rsub2 o 32.768 khz crystal output pad or external resistor node 2 by mask option. external 15~20pf capacitor connects to start oscillation and get more accurate clock when in crystal mode. ra0 ~ ra3/tone (8) i/o general input/output port specified by pm1 register. if output mode is selected, pm0 register bit 0 can be used to specify cmos/nmos driving capability option (7). initial state is input mode. ra3 may be uses as tone if bit 0 of mr0 special register is set to logic 1. an interrupt source. rb0 ~ rb3 (8) i/o general input/output port specified by pm2 register. if output mode is selected, pm0 register bit 1 can be used to specify cmos/nmos driving capability option (7). initial state is input mode. rd0 rd1/addr rd2/data rd3/clk (4) i 4-bit schmitter input port with internal pull high option specified by pm3 register bit 3. each pad has an independent interrupt capability specified by pefh special register. interrupt and stop mode wake up source. rd1~3 will be shared as the external memory w55 xxx interface pads while rd port shared as serial bus mask option is enabled. "tri-state serial bus" mask option can use to float clk/addr/spdatd while "rd port shared as serial bus" mask option is enabled. res i system reset pad, active low with internal pull-high resistor. test i test pad. active high with internal pull low resistor. rosc i connect resistor to vdd pad to generate speech or melody playing clock source. pwm1/dac o while speech or melody is active , pwm1/dac is speaker direct driving output or dac output controlled by voice output file. pwm2 o while speech or melody is active, pwm2 is another speaker direct driving output. seg0 ? seg15 o dedicated lcd segment output pads.
W536Q020/q030 publication release date: sep, 2001 - 5 - revision a1 seg16/portn.0 ? seg19/portn.3 o/o lcd segment output pads, and can be shared as general output by register lcdm3 bit 1. default function is segment pad. seg20/portm.0 ? seg23/portm.3 o/i lcd segment output pads, and can be shared as general input by register lcdm3 bit 0. default function is s egment pad and pm5.1=0 to inhibit lcd waveform abnormal. seg24/portl.0 ? seg27/portl.3 o/o lcd segment output pads, and can be shared as general output by register lcdm2 bit 3. default function is segment pad. seg28/portk.0 ? seg31/portk.3 o/i lcd segment output pads, and can be shared as general input by register lcdm2 bit 2. default function is s egment pad and pm5.0=0 to inhibit lcd waveform abnormal. seg32/portj.0 ? seg35/portj.3 o/io lcd segment output pads, and can be shared as general input/output by register lcdm2 bit 1. pm4 register is used to select input or output while shared i/o function is active. default function is segment pad and pm4.3=0 to inhibit lcd waveform abnormal. seg36/porti.0 ? seg39/porti.3 o/io lcd segment output pads, and can be shared as general input/output by register lcdm2 bit 0. pm4 register is used to select input or output while shared i/o function is active. default function is segment pad and pm4.2=0 to inhibit lcd waveform abnormal. com0 ? com7 o lcd common signal output pads either 1/16 duty or 1/8 duty. the lcd frame rate is controlled by lcdm1 register, and default value lcdm1=0111b with 64hz frame rate. com8 / portp.0 ? com11/portp.3 o/o lcd common signal output pads, or shared as general output by register lcdm3.2 when in 1/8 duty mode. default function is common function. com12/porto.0 ? com15/porto.3 o/i lcd common signal output pads, or shared as general input by register lcdm3.2 when in 1/8 duty mode. default function is common function and pm5.2=0 to inhibit lcd waveform abnormal. dh1, dh2 (5) o connection terminal for voltage double capacitor with 0.1uf. the dh2 connects to capacitor positive node and dh1 negative node if polar capacitor is used. v3 ~ v6 (5) o lcd com/seg output driving voltage. need an external 0.1uf capacitor to every pad terminal.
W536Q020/q030 publication release date: sep, 2001 - 6 - revision a1 v2 (5) i/o voltage regulator output pad. an external capacitor is a must. output level can be controlled from 0~fh by lcdm4 register. if internal pump is enabled (lcdm3.3=0 and default value), lcd operating voltage (vlcd) will be 4*v2 or 5*v2 depending on 1/4 bias or 1/5 bias. a limitation should be noted that vlcd must be higher than (vdd-0.5v) to avoid chip leakage current. while external reference voltage is selected (lcdm3.3=1), v2 pad input voltage cannot be over 1.5 volt to inhibit chip damage. vssp (6) i power ground for pwm or dac playing output. vss (6) i power ground vddp (6) i power source for pwm or dac playing output. vdd (6) i power source. (4) rd1~3 are shared as addr/data /clk to interf ace with w55xxx (5) 0.1uf is default value, and capacitor value should be larger than 0.1uf if lcd dot size over 0.5mm * 0.5mm. (6) external application circuit should connect together, please refer to application circuit. to sure chip operation properly, please bond all vdd, vddp, vss and vssp pads and connect vss and vssp from chip outside pcb circuit. (7) when working at nmos open drain mode, external pull high voltage can't higher than vdd to avoid leakage current. (8) when working at nmos open drain mode, external pull high voltage can't higher than vdd to avoid leakage current.
W536Q020/q030 publication release date: sep, 2001 - 7 - revision a1 absolute maximum ratings parameter rating unit supply voltage to ground potential -0.3 to +7.0 v applied input/output voltage -0.3 to +7.0 v power dissipation 120 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (vdd ? vss = 3.0v, no load, f m = 4 mhz with ring mode, fs = 32.768 khz, with xtal mode, t a = 25 c, stn lcd panel on with dot size 0.5mm*0.5mm; unless otherwise specified) parameter sym. conditions min typ max unit op. voltage v dd 2.4 5.5 v op. current i op1 dual clock with crystal - 600 700 ua (no load, no voice, no ) dual clock with rc type 600 700 melody) sub-clock only, lcd off 40 50 sub-clock only, lcd on 70 90 hold mode current (no load, lcd off) i op2 sub-clock active only 6 10 ua hold mode current (no load, lcd on) i op3 sub-clock active only 70 ua stop mode current i op4 lcd auto off 1 ua addr/clk output high current io h1 vout=2.7v -0.8 ma addr/clk output low current io l1 vout=0.4v 0.8 ma input low voltage v il - vss - 0.3 vdd input high voltage v ih - 0.7 - 1 vdd port ra, rb output low voltage v abl iol = 2.0 ma - - 0.4 v port ra, rb output high voltage v abh ioh = -2.0 ma 2.4 - - v ports (i, j, l, n, p) output sink current i ol3 v ol = 0.4v -300 ua pull-up resistor r d port rd 200 300 400 k ? res pull-up resistor r res - 50 100 200 k ? pwm1/2 source current (8) i sph volume option =00 -20 ma (r load =8 ? between pwm1 volume option =01 -70 and pwm2) volume option =10 -110 volume option =11 -135
W536Q020/q030 publication release date: sep, 2001 - 8 - revision a1 pwm1/2 sink current (8) i spl volume option =00 20 ma (r load =8 ? between pwm1 volume option =01 70 and pwm2) volume option =10 110 volume option =11 135 dac output current i dac vdd=3v, rl=100ohm -4 -5 -6 ma lcd supply current i lcd no load, all seg. on - 50 - a com/seg on resistor r on ioh = 50 a 5k 10k ? v2 pad output voltage v rr depended on lcdm4 0.7 1.45 v v2 pad output deviation (9) v d1 no load 5 % v2 pad voltage step v r2 lcdm4 increased 1 50 mv v6 pad output voltage (lcd's vlcd depended on v lcd 1/4 bias & no load 3.8 * v2 3.85 * v2 3.9 * v2 v lcdm4 register) (9) 1/5 bias & no load 4.75 * v2 4.8 * v2 4.85 * v2 v2 input voltage v ext lcdm3.3=1 1.5 v (8) pwm current deviation will be 20%. (9) deviation is governed by lcd dot size. more larger lcd dot will get larger deviation..
W536Q020/q030 publication release date: sep, 2001 - 9 - revision a1 ac charateristics (vdd ? vss = 3.0v, no load, f m = 4 mhz with ring mode, fs = 32.768 khz, with xtal mode, t a = 25 c, stn lcd on with dot size 0.5mm*0.5mm; unless otherwise specified) parameter sym. conditions min. typ. max. unit sub-clock frequency f sub crystal type and x32in and x32o with 17pf external cap. 32768 hz main-clock frequency f m rc type/crystal type 400k - 4m hz chip operation frequency f osc scr0.0=1,f sys =f sub 32768 hz scr0.0=0;f sys = f main 400k - 4m instruction cycle time t cyc one machine cycle - 4/f osc - s reset active width t raw fosc = 32.768 khz 1 - - s interrupt active width t iaw fosc = 32.768 khz 1 - - s main clock rc frequency f rxin rxin =680k ? 1m hz (10) rxin =330k ? 2m rxin =200k ? 3m rxin =150k ? 4m sub-clock ring oscillator f rsub r sub =680k ? 32 khz sub-clock oscillation stable time @ cold start f stop r sub =680k ? 0.8 1 s frequency deviation of main-clock f rxin 2mhz ? f f f(3v) f(2.4v) f(3v) ? 10 % frequency deviation of main-clock f rxin = 3 mhz ? f f f(3v) f(2.4v) f(3v) ? 15 % frequency deviation of main-clock f rxin =4 mhz ? f f f(3v) f(2.4v) f(3v) ? 20 % rosc frequency f rosc r osc =680k ? 3 mhz frequency deviation of f rosc = 3mhz ? f f f(3v) f(2.4v) f(3v) ? 7.5 % frame frequency f lcd lcdm1=0111 b(default) 64 hz (10) the deviation will be +20% while vdd drops from 5.5v to 2.4v based on same resistor
W536Q020/q030 publication release date: sep, 2001 - 10 - revision a1 operating current vs. main clock (rc mode) sub-clock oscillation freq vs. resistor iop vs. main clock rc mode 0 200 400 600 800 1000 1234 freq (mhz) iop (ua) 3v 4.5v oscillation freq vs. sub-clock 33.2 20 22.5 25 27.5 30 32.5 35 37.5 40 42.5 560 620 680 750 820 1k rsub (k ohm) fsub (khz) 3v 4.5v
W536Q020/q030 publication release date: sep, 2001 - 11 - revision a1 main-clock oscillation freq vs. resistor main-clock freq vs. rxin 1.11 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 130 150 160 200 330 680 2k r xin (k ohm) fmain (mhz) 2.4v 3v 4.5v 5.5v voice operating freq vs. resistor (rosc) voice operating freq. vs. rosc 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 470 560 680 910 rosc (k ohm) freq (mhz) 3v 4.5v
W536Q020/q030 publication release date: sep, 2001 - 12 - revision a1 application circuit-- 1: sub clock with rc mode com0~15 seg0~39 40seg*16com lcd panel vlcd>vdd-0.5v x32io x32in r2 vddp pwm1/dac data/rd2 clk/rd3 vss vssp w536qxxx pwm2 v2 v3 v5 v6 dh2 dh1 addr/rd1 v4 speaker q1 8050 470 ? c6 speaker (*3) (*1) (*4) (*5) w55mxx when 1/4 bias, v4=v5, c11 can skip vddp vddp vdd xin ___ res rosc r1 r4 c3 r5 switch c4 r3 c5 battery 1 2 c2 c1 (*2) (*4) rd0 ra0~3 rb0~3 vddp c12 c11 c10 c13 c14 c9 component c1 c2~c4 c5, c6 c7, c8 c9~c14 r1 r2 r3 r4 value 4.7uf 0.1uf 100pf 15~ 30pf 0.1~1uf 680k ? 680k ? 650k ? /1mhz 350k ? /2mhz 225k ? /3mhz 160k ? /4mhz 100 ?
W536Q020/q030 publication release date: sep, 2001 - 13 - revision a1 note: (1). c9~c14 depends on lcd panel dot size. (2). option r5 equals to 100 ? if high noise immunity is needed. (3). for dac option application. (4). to ensure that three batteries function well in w536f20 demo board. c 6 should stay close to pad pwm/pwm2 at its best. under the mask rom version, c 5 and c 6 can be skipped. (5). sure chip operation properly, please bond all vddp, vdd, vssp and vss; and connect vssp pad to vss from external pcb circuit. (6) main clock with ring type, the frequency deviation is depended on vdd and resistor
W536Q020/q030 publication release date: sep, 2001 - 14 - revision a1 application circuit--- 2: sub clock with crystal mode vddp pwm1/dac data/rd2 clk/rd3 vss vssp w536qxxx com0~7 seg0~39 pwm2 v2 v3 v5 v6 dh2 dh1 addr/rd1 v4 speaker q1 8050 470 ? c6 speaker (*3) (*1) (*4) (*5) 40seg*8com lcd panel vlcd>vdd-0.5v w55mxx when 1/4 bias, v4=v5, c11 can skip vddp vddp vdd xin ___ res rosc r1 r4 c3 r5 switch c4 r3 c5 battery 1 2 c2 c1 (*2) (*4) rd0 ra0~3 rb0~3 x32io x32in 32k c7 c8 vddp c12 c11 c10 c13 c14 c9 component c1 c2~c4 c5, c6 c7, c8 c9~c14 r1 r2 r3 r4 value 4.7uf 0.1uf 100pf 15~ 30pf 0.1~1uf 680k ? - 650k ? /1mhz 350k ? /2mhz 225k ? /3mhz 160k ? /4mhz 100 ?
W536Q020/q030 publication release date: sep, 2001 - 15 - revision a1 note: (1). c9~c14 depends on lcd panel dot size. (2). option r5 equals to 100 ? if high noise immunity is needed. (3). for dac option application. (4). to ensure that three batteries function well in w536f20 demo board. c 6 should stay close to pad pwm/pwm2 at its best. under the mask rom version, c 5 and c 6 can be skipped. (5). sure chip operation properly, please bond all vddp, vdd, vssp and vss; and connect vssp pad to vss from external pcb circuit. (6) main clock with ring type, the frequency deviation is depended on vdd and resistor

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